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IGNOU MCS 202 Assignment 2024 Question Paper
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- (a)Explain the von Neumann architecture. Show how an instruction is executed by the von Neumann machine.(b)Explain the main architectural differences between the von Neumann architecture and Harvard architecture with the help of a diagram of each.
(c) Perform the following conversion of numbers:
(i) Decimal (2536475891)10 to binary and hexadecimal.
(ii) Hexadecimal (FABCD1E)h to Octal.
(iii) String “ISO-8859-1 coding” to UTF 16.
(iv) Octal (23174560)O to Decimal
(d)Simplify the following function using K-map: F(A, B, C, D) = Σ (1, 3, 5, 7, 8, 12, 14, 15). Draw the circuit of the simplified function using NAND gates.
(e) Consider the Adder-Subtractor circuit given in Unit 3 of Block 1. Explain how this circuit will perform subtraction (A-B) if the value of A is 1010 and B is 1011. You must list all the bit values, including Cin and Cout and overflow condition.
(f) Explain the functioning of a 3×8 decoder. You should draw its truth table and explain its logic diagram with the help of an example input.
(g)Assume that a source data value 1001 was received at a destination as 1101. Show how Hamming’s Error-Correcting code will be appended to source data so this error of one bit is identified and corrected at the destination. You may assume that the transmission error occurs in the source data, not the error correction code.
(h)Explain the functioning of the SR flip-flop with the help of a logic diagram and characteristic table. Also, make and explain the excitation table of this flip-flop.
(i) Explain the functioning of a 3-bit ripple counter with the help of a diagram.
(j) Represent (-55.25)10 and (0.03125)10 in IEEE 754 single precision format.
- (a)Explain the logic structure of SRAM and DRAM cells. How many RAM chips of size 256K × 8 bits are needed to build a memory of size 16M Word RAM having a word size of 32 bits? Find the storage capacity of a disk with 16 recording surfaces and 32 tracks; each track has 64 sectors. You may assume that each sector can store 1 MB of data. Also, find the rotational latency of a disk which rotates at 12000 rpm.(b)Consider that the main memory of a computer is 256 words, with each word of 8 bits in size. The cache memory of this computer is 16 blocks, having a block size of 32 bits. Find the cache addresses for the main memory addresses 5Ah and 8Bh given the following cache mapping schemes:
(i)Associative cache mapping
(ii)Direct cache mapping
(iii)Two-way set associative cache mapping
(c) What is the role of the Input/Output Interface in a computer? Why are I/O interfaces needed? Explain different types of asynchronous data transfer methods.
(d)Explain the Direct Memory Access and interrupt driven I/O techniques. How are these two techniques different to each other? Also, explain different kinds of Interrupts.
(e) Explain the features and technology of the following devices:
(i) LCD Monitors
(ii) Keyboard
(iii) Voice-based Input devices
(iv) Non-impact printers
- (a)Explain the functioning of shift instructions, and subroutine call and return instructions with the help of an example/diagram of each. Also, explain the following addressing modes with the help of a diagram – Indirect Addressing and Index addressing. You should show instructions and operands in the diagram.(b)Demonstrate how the size of a machine program changes for the computation of the expression z=(a+b)*(c+d*e) when different instruction sets, having zero address, one address, two address and three address instructions, are used.
(c) Consider a machine that brings all the operands to registers before performing the ALU operation. The machine uses PC, IR, and MAR registers. All memory accesses bring data to the AX register. The operations are performed in AC and AX registers, and results are stored in the AC register. List and explain all the microoperations required to execute an instruction AC AC+[MAR] on this machine.
(d)Explain the control memory organisation and operation of the micro-programmed control unit with the help of a diagram of each.
(e) What are the features of RISC? Explain the instruction pipelining in the RISC processor. How is branch penalty handled in RISC?
- (a)Explain different components of the execution unit of the 8086 microprocessor. Compute the physical address for the following segment register: offset pairs in an 8086 microprocessor:(i) CS: IP = AAFEh: 9AAAh
(ii) DS: BX = 11FFh: 0220h
(iii) SS: SP = 5678h:89ABh
(b)How is IVT used in the 8086 microprocessor for Input/Output? Write a program using 8086 assembly language to input a string: “8086 Microprocessor was a 16-bit processor.”
(c) Write a program in 8086 assembly language, which converts a packed four-digit packed BCD number to equivalent four ASCII digits; for example, a packed BCD number “4367” stored in a word is converted to ASCII “4”, “3”, “6”, “7”. Explain the algorithm of the program.
(d)List the characteristics of the following:
(i) Parallelism in Uni-Processor Systems
(ii) Vector Processing and Array Processor
(iii) Multi-processors
(iv) Multi-core processors
(v) Cache Coherence
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